1. Field of the Invention
The present invention relates to a solid-state imaging device, a method of producing the same, and an imaging device.
2. Description of the Related Art
A method of producing a solid-state imaging device has been disclosed in which a sidewall having a three-layer structure is formed on gate electrodes of MOS transistors of the solid-state imaging device, a film (hereinafter referred to as “sidewall film”) which is the same film as the sidewall having the three-layer structure is formed on a sensor portion of the solid-state imaging device to use the sidewall film as a silicide block for preventing a silicide from forming on the sensor portion (refer to, for example, domestic re-publication of PCT international publication for patent application No. WO2003/096421 (document '421) (in particular, FIG. 64 and a description related thereto)).
However, according to the method described in document '421, in order to form source-drain regions of the MOS transistors, ion implantation for forming the source-drain regions is performed through the sidewall film having the three-layer structure. Therefore, it has been difficult to improve a short-channel effect while suppressing parasitic resistance. Furthermore, the source-drain regions are annealed in a state in which the source-drain regions are completely covered with the sidewall film having the three-layer structure, and thus stress due to the sidewall film increases (stress memorization technique (SMT), refer to, for example, K. Ota, et al., “Novel Locally Strained Channel Technique for High Performance 55 nm CMOS” IEDM Tech. Dig., pp. 27-30, 2002). Furthermore, it is assumed that it is necessary to vary the conditions for ion implantation for forming source-drain regions of MOS transistors in a logic portion from the conditions for ion implantation for forming source-drain regions of MOS transistors in a pixel portion. The reason for this is that the ion implantation for the MOS transistors in the pixel portion is performed through the sidewall film, whereas the ion implantation for the MOS transistors in the logic portion is performed without such a film. Consequently, the depth of an impurity diffusion layer of each of the MOS transistors in the logic portion differs from the depth of an impurity diffusion layer of each the MOS transistors in the pixel portion. The gate length of the MOS transistors in the logic portion is shorter than that of the MOS transistors in the pixel portion. Accordingly, it is difficult to improve the short-channel effect while suppressing junction leakage, and to suppress an increase in parasitic resistance at the same time. It is a matter of course that the ion implantation for forming the source-drain regions of the MOS transistors in the logic portion and the ion implantation for forming the source-drain regions of the MOS transistors in the pixel portion are separately performed, though this is not described in document '421.
Furthermore, when source-drain regions are annealed in a state in which a cover film that completely covers gate electrodes is provided, a tensile stress is applied to the cover film (SMT). This film stress may generate crystal defects in a silicon layer of a sensor portion, which may result in an increase in random noise and an increase in the number of white flaws and dark current.
As described above, the ion implantation for forming the source-drain regions is performed through the sidewall film. Accordingly, it is difficult to set the depth of an impurity diffusion layer to a desired value while maintaining a high ion concentration at the surface of silicon (Si). Consequently, the parasitic resistance of the source-drain regions increases, thereby decreasing a driving force of a pixel transistor.
A production method in which the above sidewall film is not used as a silicide blocking film and another film for silicide blocking is separately provided has also been disclosed (refer to, for example, Japanese Unexamined Patent Application Publication No. 2008-85104). In this production method, a silicon substrate is readily damaged by etching-back of a sidewall film for forming a sidewall on each sidewall of gate electrodes. This results in a problem of an increase in dark current. Furthermore, in this method, an oxide film disposed on a photodiode is removed before ion implantation for forming source-drain regions is performed. Accordingly, a resist mask is formed directly on the photodiode. Consequently, the photodiode is contaminated by the resist, thus increasing dark current. Furthermore, a P-type impurity in a surface area is lost due to wet etching performed on the photodiode. As a result, dark current is increased. During the wet etching for removing the oxide film on the photodiode, the amount of an upper portion of an isolation region (shallow trench isolation (STI)) in a logic portion removed by the etching is increased. Accordingly, when a silicide is formed on the source-drain regions at an edge of the isolation region in the logic portion, junction leakage due to the silicide is increased. When the oxide film on the photodiode is removed, a problem of lift-off of a part of the sidewall film becomes severe. As a result, the yield is decreased.
In a MOS transistor of a solid-state imaging device, when a sidewall having a two-layer structure is formed on each sidewall of a gate electrode, the gate electrode is formed on a silicon substrate with a gate insulating film therebetween. Subsequently, a silicon oxide film covering the gate electrode is formed on the silicon substrate. Furthermore, a silicon nitride film is formed on the silicon oxide film. Next, etching-back of the entire surface of the silicon nitride film is performed so that the silicon nitride film remains on the sidewalls of the gate electrode with the silicon oxide film therebetween. In this etching-back, the silicon oxide film functions as an etching stopper. Next, the silicon oxide film is etched. As a result, the upper surface of the gate electrode is exposed, and the silicon substrate is also exposed. In this step, the silicon oxide film formed on a photodiode of the solid-state imaging device is also removed.
In the above method, as the pixel size and the transistor size are decreased, the film thickness of the silicon oxide layer is also deceased. Therefore, in the etching-back of the silicon nitride film, it is difficult to stop the etching while the silicon substrate serving as an underlying layer is not damaged. In general, when a silicon oxide film is used as an etching stopper in etching of a silicon nitride film, it is difficult to ensure a sufficient etching selection ratio.
In addition, during the removal of the silicon oxide film, a part of the silicon oxide film located under the sidewall composed of the silicon nitride film is also removed by the wet etching. Consequently, the sidewall is in a state of lift-off by a stress due to a subsequent heat treatment or the like. The sidewall in this state may become a cause of contamination, which may result in a decrease in the yield.
When the silicon oxide film is etched, the silicon oxide film located on a photodiode of the solid-state imaging device is also removed. Subsequently, ion implantation for forming sources and drains of an nFET and a pFET is performed. In this case, a resist mask used in this ion implantation is formed directly on the photodiode. Therefore, the photodiode may be contaminated with sodium (Na) and the like contained in the resist. These contaminations may cause a problem of an increase in the number of white flaws.
FIG. 95 is a layout view of a CMOS sensor. As shown in FIG. 95, a photodiode PD and an active region 15 connected to the photodiode PD are provided on a silicon substrate. A transfer gate TRG, a reset transistor RST, an amplifying transistor Amp, and a selection transistor SEL are sequentially arranged on the active region 15. A floating diffusion portion FD is provided between the transfer gate TRG and the reset transistor RST. FIG. 96 shows an equivalent circuit of the planar layout described above. In the layout shown in FIG. 96, a pixel includes a single photodiode PD, a floating diffusion portion FD, and four transistors, namely, a transfer gate TRG, a reset transistor RST, an amplifying transistor Amp, and a selection transistor SEL. This layout shows a structure in which a plurality of photodiodes PD are shared. Alternatively, photodiodes PD may be shared, or a pixel may include three transistors instead of the four transistors.